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@article{xu2010,
	Author = {C. Xu and H. Li and R. Suaya and K. Banerjee},
	Date-Added = {2012-07-22 23:00:12 -0400},
	Date-Modified = {2012-07-22 23:01:20 -0400},
	Journal = {Electron Devices, IEEE Transactions on},
	Title = {Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs},
	Volume = {57},
	Year = {2010}}

@inproceedings{Alam2007,
	Author = {Alam, S.M. and Jones, R.E. and Rauf, S. and Chatterjee, R.},
	Booktitle = {Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on},
	Owner = {quz106},
	Timestamp = {2012.05.04},
	Title = {Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology},
	Year = {2007}}

@inproceedings{Bandyopadhyay2009,
	Author = {Bandyopadhyay, T. and Chatterjee, R. and Daehyun Chung and Swaminathan, M. and Tummala, R.},
	Booktitle = {Electrical modeling of Through Silicon and Package Vias},
	Owner = {quz106},
	Timestamp = {2012.06.26},
	Title = {3D System Integration, 2009. 3DIC 2009. IEEE International Conference on},
	Year = {2009}}

@article{Cho2011,
	Author = {Jonghyun Cho and Eakhwan Song and Kihyun Yoon and Jun So Pak and Joohee Kim and Woojin Lee and Taigon Song and Kiyeong Kim and Junho Lee and Hyungdong Lee and Kunwoo Park and Seungtaek Yang and Minsuk Suh and Kwangyoo Byun and Joungho Kim},
	Journal = {Components, Packaging and Manufacturing Technology, IEEE Transactions on},
	Owner = {quz106},
	Pages = {220-233},
	Review = {Coupling model: a 3D transmission line matrix method Method: first model (also use S parameter), then build a via last test vehicle for measurement More references: 6-10 Two new coupling paths: TSV-TSV coupling and TSV-active circuit coupling Noise coupling between TSVs: The skin depth of TSV will affect the resistance after 20MHz which increase the resistance over 16 times. Total 11387 lumped circuit elements are used for model one TSV-TSV test vechicle Noise coupling between TSV and substrate contact: Mutual inductance is removed because there is no ground TSV for the TSV-substrate conact coupling. At low frequency, C tsv dominates, and higher, R sub dominates. Much higher, C sub dominates (TSV to sub contact). TSV-TSV: A, C tsv, B, C sub; C, R sub},
	Timestamp = {2012.05.04},
	Title = {Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring},
	Volume = {1},
	Year = {2011}}

@inproceedings{Katti2010a,
	Author = {Katti, G. and Mercha, A. and Stucchi, M. and Tokei, Z. and Velenis, D. and Van Olmen, J. and Huyghebaert, C. and Jourdain, A. and Rakowski, M. and Debusschere, I. and Soussan, P. and Oprins, H. and Dehaene, W. and De Meyer, K. and Travaly, Y. and Beyne, E. and Biesemans, S. and Swinnen, B.},
	Booktitle = {Interconnect Technology Conference (IITC), 2010 International},
	Owner = {quz106},
	Review = {Depletion behavior of TSV can be exploited to reduce TSV capacitance at higher temperature. Measurement: 2D/3D ring Oscillator, capacitance, leakage and resistance focus on the depletion capacitance between doped substrate and TSV liner. The consistent increase in Ctsv with temperature should be taken into account in the lumped RC model for circuit simulations. empirical TSV capacitance estimation: C(T) = 0.0007T^2 - 0.0333T + 44.4 The temperature has limited impact on TSV leakage increment.},
	Timestamp = {2012.06.26},
	Title = {Temperature dependent electrical characteristics of through-si-via (TSV) interconnections},
	Year = {2010}}

@article{Katti2010,
	Author = {Katti, G. and Stucchi, M. and De Meyer, K. and Dehaene, W.},
	Journal = {Electron Devices, IEEE Transactions on},
	Owner = {quz106},
	Pages = {256-262},
	Timestamp = {2012.05.04},
	Title = {Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs},
	Volume = {57},
	Year = {2010}}

@article{Katti2011,
	Author = {Katti, G. and Stucchi, M. and Velenis, D. and Soree, B. and De Meyer, K. and Dehaene, W.},
	Journal = {Electron Device Letters, IEEE},
	Owner = {quz106},
	Pages = {563-565},
	Review = {Other references: 5-7 Method: semianalytical (fundamental electrostatic principles), verified with electrical measurement Conclusion: higher oxide thickness, low doped substrates reduce the impact of temp. rise on TSV Capacitance. The sensitivity of TSV capacitance to temp. is high. The behavior of TSV in 3D IC is similar to a MOS capacitor. The analytical expression for TSV capacitance is derived by solving the 1D poisson equation. At room temperature, the densities of electron and hole charges are less than the acceptor ions in the substrate, however, at higher temperature, the densities of hole and electron should not be neglected. Method by calculating the depletion radius step by step until it converges (< 1nm). The rise in TSV capacitance with increasing temperature is because of the maximum depletion radius due to high electron concentration. The percentage increase in capacitance is less for TSVs with higher oxide thickness. An optimal substrate doping concentration exists for a minimal TSV capacitance.},
	Timestamp = {2012.05.04},
	Title = {Temperature-Dependent Modeling and Characterization of Through-Silicon Via Capacitance},
	Volume = {32},
	Year = {2011}}

@inproceedings{Khalil2008,
	Author = {Khalil, D.E. and Ismail, Y. and Khellah, M. and Karnik, T. and De, V.},
	Booktitle = {Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on},
	Owner = {quz106},
	Review = {Goal: find an analytical model for the propagation delay of TSVs as a function of the physical dimensions. Delay of TSV td = f(l, r, s, delta, epson, mu) delta: conductivity of the TSV material epson: electric permittivity of the dielectric material surrounding the TSV mu: the magnetic permeability of the material surrounding the TSV TSV delay simulation: electromagnetic field solution and circuit simulation For short enough transmission lines, the damping factor is small, and hence the inductance is dominant. For long enough transmission lines, the damping factor is large, and hence the resistance is dominant. The propagation delay is proportional to the RC time constant. RC delay model is highly inaccurate due to the significant presence of inductance in TSVs.},
	Timestamp = {2012.05.04},
	Title = {Analytical Model for the Propagation Delay of Through Silicon Vias},
	Year = {2008}}

@inproceedings{Khan2009,
	Author = {Khan, N.H. and Alam, S.M. and Hassoun, S.},
	Booktitle = {3D System Integration, 2009. 3DIC 2009. IEEE International Conference on},
	Owner = {quz106},
	Review = {This paper exams the TSV induced noise to device and other TSVs in two substrates, one kind is high-R substrate which is normally used for low performance dies such as memory; the other is EPI substrate which is used for processors. They built a SPICE-based model for the simulation. The grid size is fixed as 0.5 um by comparing the results from SPICE model and FEM solver. 1. The effect of backside GNP plane to power noise is analysis. Without GND plane, the peak body voltage is high for both substrates. For EPI substrate, the impact is larger. While with backside GND plane, the peak body voltage can be suppressed and EPI can achieve less than 20% noise when the distance between device and TSV is larger than 2um. 2. For TSV-to-device noise characterization, they varied the signal slew rate, sidewall ILD thickness and TSV height to see how these parameters affect the peak body voltage. 3. For TSV-to-TSV noise characterization, the variables are TSV spacing, sidewall ILD thickness and TSV height. At last they examed the noise mitigration effect using coaxial TSV. The peak body and TSV voltage noise can be less than 0.01V with 1V supply voltage in both substrates when the coaxial TSV and backside GND plane are both applied.},
	Timestamp = {2012.07.13},
	Title = {Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs},
	Year = {2009}}

@inproceedings{Majeed2010,
	Author = {Majeed, B. and Sabuncuoglu Tezcan, D. and Vandevelde, B. and Duval, F. and Soussan, P. and Beyne, E.},
	Booktitle = {Electronics Packaging Technology Conference (EPTC), 2010 12th},
	Owner = {quz106},
	Review = {method: measurement of built wafer full wafer electrical characterization based on resistance of Kelvin and daisy chain structures Due to hypo-elastic properties of polymer, sometimes thick polymer can absorb some stresses. The first interface delamination starts at the point where polymer is thinnest Cumulative yield of a single TSV for the batch of 5 wafers?? After thermal cycling test, the fail wafers are measured through FIB, one of the main factors contributing the failure could be repeated testing on copper measuring pads.... The resistance of a single TSV indcluding metal contact is in range from 5~20 mOhms. 75MPa is the minimum adhesion strength required to avoid delamination.},
	Timestamp = {2012.05.04},
	Title = {Electrical characterization, modeling and reliability analysis of a via last TSV},
	Year = {2010}}

@inproceedings{Pak2007,
	Author = {Jun So Pak and Chunghyun Ryu and Joungho Kim},
	Booktitle = {Electronic Materials and Packaging, 2007. EMAP 2007. International Conference on},
	Owner = {quz106},
	Review = {Use both structural parameters and the material parameters Usually, an interconnection line is characterized using S-parameters S21. In order to use TSV in high speed system over 10 Gpbs, the large capacitance problem of TSV must be solved by increasing SiO2 thickness between TSV and silicon substrate, which means reducing capacitance of TSV. and reducing TSV height is very helpful to keep eye open area wide by adopting thinner TSV stucture. Frequency domain (S-parameters) and time domain ( eye diagrams) as TSV size is larger, total resistance is smaller, but the signal loss is the largest due to wider faced area. The highest TSV has largest total resistance and capacitance. Pitch is critical for making the eye area small. For a higher frequency application, a higher resistivity silicon substrate embedding TSV must be selected. For cross-talk, two signal TSV should be far away from each other.},
	Timestamp = {2012.05.04},
	Title = {Electrical characterization of through silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation},
	Year = {2007}}

@inproceedings{Roullard2011,
	Author = {Roullard, J. and Capraro, S. and Farcy, A. and Lacrevaz, T. and Bermond, C. and Leduc, P. and Charbonnier, J. and Ferrandon, C. and Fuchs, C. and Flechet, B.},
	Booktitle = {Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st},
	Owner = {quz106},
	Review = {Interconnects have four groups: 1. inter-chip interconnects (Cu-Pillar, micro-bumps) 2. intra-chip interconnects (TSV) 3. backside interconnects (RDL) 4, on-chip interconnects (BEOL) low density/ high density according to the diameters RDL: List the distributed parameters of the electrical model of RDL transmission line (skin effect??) BEOL model: RLCG values are given (G?) TSVs: the ABCD?? matrix of TSV is extracted from measured ABCD matrices of RDL, BEOL, and DUT. inter-die connections: Cu-Pillars: first Cu layer, a SnAg layer and a second Cu layer RDLG values are given, can be used for verification Study objective: 1. determine the best layer (RDL or BEOL) to transmit signals depending on distance RDL routing causes a marked decrease in the delay. For 2 mm length delay is reduced by about 60% 2. stacking strategy: F2F or F2B: results are not clear!! the saving of delay can come up to 80% when the length exceeds 8mm 3. Technological strategy: test five chains with interconnects with different parameters. Normally, when the interconnect length increases, the delay of RDL dominates, otherwise, TSV delay dominates the total delay.},
	Timestamp = {2012.05.04},
	Title = {Electrical characterization and impact on signal integrity of new basic interconnection elements inside 3D integrated circuits},
	Year = {2011}}

@inproceedings{Ryu2005,
	Author = {Chunghyun Ryu and Daehyun Chung and Junho Lee and Kwangyong Lee and Taesung Oh and Joungho Kim},
	Booktitle = {Electrical Performance of Electronic Packaging, 2005. IEEE 14th Topical Meeting on},
	Owner = {quz106},
	Review = {Using RLCG components, parameters are fitted to the measured S-parameters up to 20GHz Time domain verification: Metrics: time domain reflectometry, and time domain transmission, eye-diagram waveforms Measurement: TDR/TDT using Tektronix; eye-diagram measurement using psuedo random bit sequence signal generator and sampling oscilloscope To guarantee the data quality over Gbps bandwidth, the capacitance of the via should be reduced.},
	Timestamp = {2012.05.04},
	Title = {High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package},
	Year = {2005}}

@inproceedings{Salah2011,
	Author = {Salah, K. and El Rouby, A. and Ragai, H. and Amin, K. and Ismail, Y.},
	Booktitle = {Circuits and Systems (ISCAS), 2011 IEEE International Symposium on},
	Owner = {quz106},
	Timestamp = {2012.05.04},
	Title = {Compact lumped element model for TSV in 3D-ICs},
	Year = {2011}}

@article{Savidis2009,
	Author = {Savidis, I. and Friedman, E.G.},
	Journal = {Electron Devices, IEEE Transactions on},
	Owner = {quz106},
	Pages = {1873-1881},
	Timestamp = {2012.05.04},
	Title = {Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance},
	Volume = {56},
	Year = {2009}}

@inproceedings{Weerasekera2009,
	Author = {Weerasekera, R. and Grange, M. and Pamunuwa, D. and Tenhunen, H. and Li-Rong Zheng},
	Booktitle = {3D System Integration, 2009. 3DIC 2009. IEEE International Conference on},
	Owner = {quz106},
	Review = {(field solver derived values as comparison, quasi-static electromagnetic-field solver) A thin annular TiN layer is usually deposited between the Cu and SiO2 layers, which acts as an adhesion layer and also concentrates the current in the Cu bar due to its high resistivity. the coupling terms to the non-adjacent TSVs are negligible. 7x7 -> 3x3 TSVs bundle Inductive coupling is long range and therefore the inductance matrix is well populated, with all elements being non-negligible.},
	Timestamp = {2012.05.04},
	Title = {Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits},
	Year = {2009}}

@inproceedings{Wright2006,
	Author = {Wright, S.L. and Polastre, R. and Gan, H. and Buchwalter, L.P. and Horton, R. and Andry, P.S. and Sprogis, E. and Patel, C. and Tsang, C. and Knickerbocker, J. and Lloyd, J.R. and Sharma, A. and Sri-Jayantha, M.S.},
	Booktitle = {Electronic Components and Technology Conference, 2006. Proceedings. 56th},
	Owner = {quz106},
	Timestamp = {2012.05.04},
	Title = {Characterization of micro-bump C4 interconnects for Si-carrier SOP applications},
	Year = {2006}}

@article{Wu2012,
	Author = {Xiaoxia Wu and Wei Zhao and Nakamoto, M. and Nimmagadda, C. and Lisk, D. and Gu, S. and Radojcic, R. and Nowak, M. and Yuan Xie},
	Journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
	Owner = {quz106},
	Pages = {186-191},
	Timestamp = {2012.05.04},
	Title = {Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs},
	Volume = {20},
	Year = {2012}}

@inproceedings{Xie2009,
	Author = {Jianyong Xie and Daehyun Chung and Swaminathan, M. and Mcallister, M. and Deutsch, A. and Lijun Jiang and Rubin, B.J.},
	Booktitle = {3D System Integration, 2009. 3DIC 2009. IEEE International Conference on},
	Owner = {quz106},
	Review = {The electrical and thermal fields in 3D systems are fully coupled together. The IR drop in 3D PDN (power delivery network) will be affected by non-uniform thermal distribution in the whole system. The electrical and thermal fields are coupled and affect each other (through joule heating?). In the analysis, the thermal conductivities of conductors and dielectrics are considered as constant for simplicity... Analysis steps: 1. input the geometry related information and solve the steady state electrical 2. heat source (joule heating) calculation from power distribution 3. steady state thermal solving 5. update electrical resistivity of conductors 6. if not converged, go to step 2 The temperature effect on the IR drop in CPU1 is 23% increase. The results show that the temperature effect on IR drop should be considered to obtain accurate DC drop.},
	Timestamp = {2012.06.27},
	Title = {Electrical-thermal co-analysis for power delivery networks in 3D system integration},
	Year = {2009}}

@inproceedings{Xu2009,
	Author = {Chuan Xu and Hong Li and Suaya, R. and Banerjee, K.},
	Booktitle = {Electron Devices Meeting (IEDM), 2009 IEEE International},
	Owner = {quz106},
	Timestamp = {2012.06.26},
	Title = {Compact AC modeling and analysis of Cu, W, and CNT based through-silicon vias (TSVs) in 3-D ICs},
	Year = {2009}}
